By definition, a microprocessor is a single chip: or at most a very few, closely-integrated, chips. The characteristics of chips affect what we can, and cannot, successfully incorporate in the architecture/organisation of microprocessors.
Silicon chips are small rectangles of silicon, typically up to about 4 or 5 square cm in area at the moment. The maximum (economic) size of chips has been steadily rising, for reasons we will consider later. There are many ways in which we can make silicon chips: in some, the silicon itself simply acts as a base on which the chip is built; but in most it plays some part in the electrical operation of the device.
The chip is made up of a number of layers built-up on one side of the silicon rectangle. The lower layers interact to form the active components – usually transistors. The upper layers form the passive components – usually wires. Around the edges of the chip, are pads: (relatively) large areas of metal, used to connect to the outside world.
As the size of chips has steadily grown, so the size of the features that make up their layers has fallen. Currently, the minimum feature size for commercial chips is 65 to 90 nanometers. 45 nanometers is expected in 2007/2008. Typically, for microprocessor-type chips, we can fit (at the moment) around a billion (1000 million) transistors on a chip – though most current processors have significantly fewer. For comparison, a simple logic gate can be constructed with from 2 to 10 transistors; a simple memory circuit with from 1 to 12 transistors. Clearly, 1000 million transistors allows us considerable scope.
Pure silicon is an insulator which is not especially useful. However, if we add certain elements (technically, impurities) to silicon – a process known as doping – we can increase the number of free charge carriers (charged particles that are free to move about within the silicon), and are hence enable it to carry an electrical current. The result of this is that silicon becomes progressively more conductive (i.e. becomes a semiconductor) the more impurity is added.
The type of impurity affects the type of charge carrier. Some doping impurities generate free electrons – negative charge carriers. Such doped silicon is called n-Type. Others generate holes – spaces where electrons should be. Although not strictly `particles' these holes behave like positive charge carriers.
The current dominant silicon technology is CMOS – complementary metal oxide semiconductor. Originally, CMOS was mainly a low-power technology, used for devices like digital watches and calculators – not computers, because it was too slow. However, considerable work went into developing it because of its recognised potential.
To explain how a CMOS transistor works, consider a piece of p-Type silicon with a layer of insulator and a conducting plate. Now apply a positive charge to the plate. Most of the charge carriers in the p-Type silicon are holes, but there will still be significant number of electrons – the minority charge carriers. The positive charge on the conducting plate will repel the holes and attract the electrons – forming a negatively charged region beneath the plate. See figure 17.1, which shows the components in cross-section.
If we now embed two n-Type regions within the p-Type silicon, on either side of the conducting plate, the negatively-charged region acts as a conducting path provided the positive charge is present. When the charge is removed, the negatively charged region will disperse and the conducting path will be broken. This is essentially how an n-Type transistor operates. See figure 17.2. A p-Type transistor is just a reversed version – with p-Type silicon and a negative charge on the conducting plate.
The embedded regions form the source and drain of the transistor (see chapter 15 for a reminder of transistor technology). Because they were traditionally manufactured by a process of diffusing ions into the surface layers of the silicon, such areas are traditionally called diffusion. Currently, such regions are often made from a mixture of silicon and metal (which has lower resistance, allowing signals to travel faster). The insulator between the silicon and the conducting plate is silicon oxide (glass, essentially). The conducting plate, or gate, itself is traditionally polycrystaline silicon, or `poly'. This is silicon without a uniform crystal structure (unlike the silicon substrate on which the chip is made). Again, this is commonly replaced by a mixture of silicon and metal which has lower resistance.
These so-called active layers of the chip form the transistors – the `active' components. We also need passive components – wires essentially – to connect transitors together. These are made from metal layers, which are separated from each other and the active layers by silicon oxide. Holes are made in the silicon oxide (contacts, or vias) to make connections between the layers. There may be many wiring layers in modern chips. Traditionally, the metal used was aluminium, but copper is becoming very common (again because of lower resistance). A small circuit representing an inverter, is shown in figure 17.3.
If you are reading this on-line, in figure 17.3, metal is blue, polysilicon is red, n-Type diffusion is green, p-Type diffusion is yellow, and contacts are black. (And if you are not reading on-line, there are labels – `n', `p', `poly', `metal' – we will get back to the `w's in section 17.6.) These colours are `traditional'. If In is high, then the n-Type transistor (on the left) is on – that is, the two (green) regions marked `n' are connected. This means Out is connected to Ground; hence Out is low. If In is low, then the p-Type transistor (on the right) is on – the two (yellow) regions marked `p' – are connected. This means that Out is connected to Power; hence Out is high.
(If you are familiar with `conventional' transistors, the names and properties may seem strange. CMOS transistors are field-effect transistors (FETs, or MOSFETs) instead of the more usual junction transistors. Hence the different names – gate, source and drain instead of base, collector and emitter. The major difference between field-effect and junction transistors is that field-effect transistors are bidirectional. That is, current can flow either from source to drain, or vice versa. In a junction transistor, current can only flow from emitter to collector.)
Chips consist of a number of layers, each of which is manufactured in turn. Some of the details of each layer differ, but a common part of the process is masking. The surface of the partially-manufactured chip is covered with a layer of light-sensitive material called photoresist. It is then exposed to UV-light through a photographic mask representing the layer being manufactured, or an electron beam `draws' the components of the layer. This process induces changes in the photoresist, which is selectively removed by some solvent: either those parts of the photoresist exposed to the light/electron beam (positive photoresist), or those parts not exposed (negative photoresist), are removed. This exposes parts of the chip surface, which can then be processed in various ways. The usual manufacturing steps are as follows.
On the face of it, it would seem that we could make chips as big as we wish – why are we restricted to 4 to 5 square cm?
First, because the manufacturing process is not perfect. Chips are made in batches on circular silicon wafers: usually 20 to 30 cm in diameter, at present. After manufacture, the wafers are cut up and the individual chips packaged. However, the silicon wafers will have a number of flaws: also, the manufactured layers on the chip surface may have faults. The larger the chip, the more chance there is of one of these flaws falling within its boundary, and stopping it working. Also, fewer large chips will fit on a wafer – so there are fewer possible `good' chips in the first place. Manufacturers are (obviously) keen to maximise the proportion of working chips (some will fail), and there is an economic upper bound to the size of a chip that can be made for a particular cost.
The second reason is to do with power dissipation. A typical modern microprocessor will dissipate tens of watts. This is a very significant amount, given the small surface area: remember the lightbulb thought experiment in chapter 2. To keep chips cool enough to work, substantial heat sinks and fans are needed: the larger the chip, the larger the potential power dissipation. (And remember, that CMOS is a low power technology.)
Integrating an entire processor onto a single chip has many advantages. First, the components are closer together, which means they can run faster: in general, shorter communication paths are quicker. As the minimum feature size shrinks, so do certain unhelpful electronic properties (essentially capacitance), allowing yet faster clock rates.
However, there are also some restrictions. The chip area, and transistor counts, now available are large: however, they are by no means unbounded. Consequently, the available real estate (space, basically) is limited, and our processor has to fit within it. Chips are, by nature, flat. Although there are wiring layers available, it is not a good idea to incorporate too many long wires (e.g. a few mm or more) into chips. Capacitance means that signals travelling down such wires may be unacceptably slow, resulting in lower clock rates. (Resistance is also a potential problem – though for the usual wiring material (metal) this is usually very low.)
Although there are techniques for speeding up the transmission of data down such wires, they take up space and use power. Basically, we can build special driver circuits whose sole function is to drive signals down long wires using large amounts of current, or by modifying logic circuits to do the same. For example, in figure 17.3, if we increase the widths `w', then the inverter will supply more current (using more power, taking up more space). More current means the capacitance of any wire connected to the inverter will charge (or discharge) more quickly.
The net result is that some architectures map to silicon better than others. For example, suppose we came up with a very elegant, and in principle fast, architecture, that we represent as a 3D diagram. Unless we can find an efficient way to map that architecture to 2D, where there are few or no connections between components that are not physically next to each other, then the theoretical benefits may not be realised.
The pads that are used to connect chips to the outside world are placed around the edge of the chip. This limits where we can place IO components: for example, if we put one in the middle, we will have to run long wires to the IO pads on the outside of the chip.
The International Technology Roadmap for Semiconductors, a set of documents dealing with current and anticipated future research in this industry, predicts that after 45nm processes, the next milestone will be 32nm, then 22nm, anticipated for around 2011. Interestingly, due to physical factors, it is expected that in order to achieve this, manufacturers will have to evolve past the current `many flat layers' approach, to a situation in which the transistor elements protude from the plane of the chip (so called `FinFETs'). This will represent a fairly major change in manufacturing process, and it remains to be seen if this actually going to fly or not.
Figure 17.4 shows the basic internal layout of a simple data unit, with a single IO port at the left-hand side. This kind of data unit is now outdated, and we would not use such a layout in a modern, high-performance microprocessor. However, it illustrates a few key points. The design consists of a number of registers, an ALU, an ALU output buffer (also a register), and the IO port. Each register is made up of a number of single-bit register cells, each of which is replicated as many times as necessary to get the required number and width of registers. In this case, there are six 8-bit registers. Similarly, The ALU, buffer, and IO ports are made up of replicated single bit cells. A single-bit horizontal segment of the data unit is called a bit slice. Within each cell, the arrangement of data and control signals is also shown in figure 17.4.
Notice that signals enter and leave cells at the same points on opposite sides, and that data and control are orthoganol – they run at right angles to each other. Also notice that the vertical dimensions of the register and ALU cells are the same, to ensure that they fit together well in a uniform array. This is called pitch matching. Pitch matching and ensuring that inputs/outputs line up on either side of a cell allows the design to be layed-out by simply tiling the plane, with no intervening wiring. Also note that there are not many individual cell designs. We have constructed a relatively few number of individual cells and replicated them, which is obviously an efficient use of a designer's time.
Control circuitry can be commonly constructed using a programmable logic array (PLA). A PLA is based on the observation that any boolean function can be transformed into either disjunctive or conjunctive normal form – either the OR of ANDs, or the AND of ORs – and thence, by de Morgan's Laws, into the NOR of NORs. A PLA allows the systematic implementation of many such Boolean expressions in parallel, and can be (semi) automatically constructed. The basic structure of such a PLA, suitable for controlling a data unit, is shown in figure 17.5.
Inputs are clocked into the input register and then their inverses are generated. The inputs and inverses are then fed into the first NOR gate plane. This is a vertical stack of gates which compute the NOR of arbitrary combinations of inputs and inverses. These results are fed into the second NOR gate plane, before being clocked into the output register. Hence a PLA can compute an arbitrary number of Booleans expressions of a large number of inputs simultaneously. There are limits on the size of PLAs imposed by physical/electrical properties. However, PLAs can be sub-divided to overcome these limits. In practice, PLAs are generated automatically from the Boolean expressions required, reducing the likelihood of implementation errors. A large number of software tools are available to manipulate and minimise PLAs.